System for multiple output of spoken messages



Sept. 28, 1965 SYSTEM FOR MULTIPLE OUTPUT 0F SPOKEN MESSAGES Filed June6, 1961 W. K. FRENCH FIG.|

3 Sheets-Sheet 1 OUTPUT CHANNELS A TTORNE Y6 3 Sheets-Sheet 2 W. K.FRENCH SYSTEM FOR MULTIPLE OUTPUT OF SPOKEN MESSAGES Sept. 28, 1965Filed June 6, 1961 same 25;

Sept. 28, 1965 w. K. FRENCH SYSTEM FOR MULTIPLE OUTPUT OF SPOKENMESSAGES Filed June 6, 1961 3 Sheets-Sheet 3 l 2E @258 8028525 fi 8E;02% on QEQ mo mo dill mm o S J 2% m mm mo a Cum 2 & E1; :20 @7223 n. N-E0; 202 w 29mm 2525 V N m o 1 95 52,: 9mm 8! E; 75; mm Tam r mo m 228 mm6 5%; 052 N k: o P M2: 02% 55% M92 E; 1. ME 525 mm 9 a 08 5 50d m2: 3:5525 Eza 8\ United States Patent 0 3,209,074 SYSTEM FOR MULTIPLE OUTPUT 0FSPOKEN MESSAGES Walter K. French, Montrose, N.Y., assign-or toInternational Business Machines Corporation, New York, N.Y., acorporation of New York Filed June 6, 1961, Ser. No. 115,228 6 Claims.(Cl. 179-1) This invention relates to a system for the multiple outputof spoken messages and more particularly to such a system in which aplurality of messages is composed from a reservoir of audio words andthese message compositions are done simultaneously for a plurality ofoutput message channels whereby each channel may contain an entirelydiflFerent message.

Systems are known in which a number of different speech messages areseparately stored on diflerent tracks of a constantly rotating drum inwhich control signals select one of these messages for transmission.Systems are also known in which a plurality of speech sounds are storedon a rotating drum and coded signals are used to synthesize the speechspecified by the code. However, this invention is directed to thesynchronous sampling of, individual speech sounds stored in individualtracks on a constantly rotating drum so that individual speech messagesare composed and gated simultaneously to a plurality of selected outputchannels. Such is the broad object of this invention.

A further object is to achieve such a system while employing timedivision multiplexing or switching whereby the quantity of switchingequipment is minimal.

These objects as well as others are achieved simultaneously inaccordance with the present invention by a system for composing speechmessages in a plurality of output channels, said messages being composedof at least one word that comprises means to store words in the form ofaudio signals at discrete addresses in a word storage device, means tostore selected discrete addresses in a word address storage device,means to address said word storage device with said selected discreteadrcsses in accordance with a predetermined time multiplex sequence,means to condition said output channels to receive said words inaccordance with said predetermined sequence, means to gate portions ofsaid words as determined by said discrete address to said outputchannels whereby said predetermined repetitive sequence of addressingand gating results in the composition of said speech messages in saidoutput channel.

Other objects and advantages of the invention will be pointed out in thefollowing description and claims and illustrated in the accompanyingdrawings, which disclose, by way of example, the principles of theinvention and the best mode which has been contemplated of applyingthese principles.

In the drawings:

FIGURE 1 is a block diagram showing the system constructed in accordancewith the present invention; and

FIGURES 2A and 2B comprise a diagrammatic representation of thecomponents of the system constructed in accordance with the presentinvention.

Referring first to FIGURE 1, a constantly rotating drum has storedthereon in real time a plurality of words in audio signal form.Preferably there is one word per drum track. Each signal starts at thesame time location on the drum and the beginning of each of the words istime related to a drum sync pulse preferably stored on a separate synctrack. The sync pulse is fed to a computer or the like which responds bysending to the drum register a seven-bit word address which is todesignate one of the word tracks on the drum.

The transfer of this first word address to the drum register initiatesthe operation of the control circuits. These control circuits perform anumber of functions. Among these functions are the following: First, thescanner ring is stepped to store each successive word address receivedby the drum register into the core array. Second, the drum register isreset after each of the word addresses therein has been stored in thecore array. Third, after the storage of each of the word addresses inthe core array, the computer is ordered to send another word address tothe drum register.

Ultimately, a plurality of word addresses is stored in the core array.Now, the stepping of the scanner ring reads out each of the wordaddresses to the drum register and the contents thereof are decoded bythe decoding matrix. This matrix functions to gate a portion of aselected word from the drum to a selected output channel determined bythe scanner ring. Output gating circuitry functions to accomplish this.As each word address is read out of the core array to the drum registerand is decoded by the matrix, it is also read back into the core array.Repetition of this reading out process with the resultant repetitivesampling of selected words in the form of audio signals on designateddrum tracks results in the composition of selected words in audio formin the output channels. Repeated loading and readout of the core arrayresults in multiword messages in these output channels.

It should be noted that the word addresses are read out from the corearray in a predetermined repetitive sequence as determined by thescanner ring and its connections to the core array. The scanner ringalso establishes this predetermined sequence for conditioning the outputchannels. For instance, the word addresses in the array may be read outfrom the first word stored therein to the fiftieth word. As the firstaddress is read out for decoding and addressing of the drum, the firstoutput channel is simultaneously conditioned to receive that portion ofthe drum word which is so addressed. This portion may come from any oneof the tracks on the drum, the particular track being determined by thecontents of the drum register being decoded by the decoding matrix atthat instant of time. By virtue of this scheme, time multiplexing orswitching is achieved. In other words, during the first period of time aportion of the first word for channel 1 is gated to channel 1. Duringthe second period of time, the first portion of the word for channel 2is gated to channel 2. If there are, for instance, fifty outputchannels, then during the first fifty periods of time each channelreceives the first portion of the first word ultimately to beincorporated into the message for said channel. During the second fiftyperiods of time, the second portion of each of the words is gated toeach of the output channes. By repeating this process the first word ineach of the messages for each of the output channels is composed. Thesecond Word for these messages is similarly composed. Ultimately, aftera number of these sequences, the entire message for each of the channelsis composed.

Referring to FIGURES 2A and 2B, the word drum 10 contains a plurality oftracks thereon. In one particular embodiment there are 128 word tracksand one sync track. Words in the form of audio signals at real time areindividually stored on the tracks, one word per track. There are aplurality of output channels which are identified herein from channel 1to channel 50. By means to be explained, messages composed of aplurality of words selected from the drum tracks are composed and aresimultaneously made available at the output channels. For instance,channel 1 may provide message 1, channel 2 may provide message 2, etc. Atypical ap plication of this invention is in a stock quotation system.For instance, channel 1 may read out the fact that stock A is presentlyquoted at 12%. At the same time, channel 2 may readout that stock B ispresently quoted at 25 /2. Means not shown may be provided forconnecting to any one of the output channels depending upon the stock ofinterest.

The drum rotates at one revolution per second. Therefore, each word inthe 128 tracks is made available once per second. All the audio signalsconstituting the words start at the same instant of time during therevolution, said time being correlated with the sync pulse in the 129thtrack. The outputs from the audio tracks on the drum are fed to theaudio amplifiers WAl through WA128. There are 128 analog gates which areidentified here as word gate 1 (W61) through word gate 128 (WG128). Theoutputs of all of these gates feed a common bus 11. This bus connectswith analog gates associated with each of the output channels and hereidentified as 12 through 15. Low pass filters 12a-15a are employed torecover the audio signals from a sample data sequence. The use of suchfilters is conventional and is described in: Radio Telemetry," Secondedition, by M. H. Nichols and L. L. Rauch, published by John Wiley &Sons, copyright 1956, with specific reference to chapter 16.

To better understand the operation of the inventive system, saidoperation has been divided into two parts; namely, (1) loading wordmemory and (2) readout from word memory.

(1) Loading word memory When the drum sync pulse is received from track129 of the drum at the output of the pulse amplifier 16, it generates acommand which instructs computer 18 to provide seven-bit addresses to beloaded into the word memory. The drum sync pulse also conditions controlcircuitry to enable the loading process as follows: The drum sync pulseresets flip-flop 1 (FFl), and flip-flop 2 (FF2) and sets flip-flop 3(FPS). The drum sync pulse through each of the OR gates 19 through 22associated with the word memory core array 23, resets all of the coresin the word memory core array 23, which is used to store the addresswords. There is one read and one write driver for each row of cores.This word memory core array is composed of a 7 x 50 array of two-statecores. In this particular instance, the dimensions are determined by thefact that there are 50 output channels to be serviced and the codeemployed in the system to designate the address Words identifying therespective audio tracks is a seven-bit code. The outputs of the OR gates19 through 22 feed their associated read drivers, each of which providesfull reset current to the associated cores. The set state of fiip-flop 3de-conditions AND gate 26 so that the AUDIO SAM- PLE LINE is down toinhibit the decoding matrix 36. The drum sync pulse also turns on theRD-l stage of the scanner ring 28.

Now all of the cores in the word memory core array 23 have been reset.Flip-flops 1 and 2 have also been reset and flip-flop 3 has been set.The one megacycle clock 24 which is continuously in operation issupplying its output pulses to gate 25 but gate 25 is blocked becausefiip-flop 1 is reset.

The drum sync pulse generates the signal START WORD TRANSFER in thecomputer which responds by sending the first seven-bit word into drumregister 27. This computer word is not to be confused with the audiowords on the drum. The computer supplied word is actually a drum trackaddress. The first computer word is now in register 27.

FF3 provides the signal READ INHIBIT LEVEL. While the line READ INHIBITLEVEL is up during loading of word memory, all sense amplifiers 41-47are inhibited by this signal through OR gate 50.

At the time that this first computer word is transferred from thecomputer to register 27, the line COM- PUTER LOADS DRUM REGISTER goes upto set fiipflop 1 to unblock gate 25. The unblocking of gate allowsclock pulses from generator 24 to pass to the control circuitry. Thisgate supplies a scanner ring stepping pulse to the scanner ring 28. Thefirst stage of the scanner ring is identified as RD-l or read 1. It hasbeen turned on by the drum sync pulse. Therefore, the first pulse fromthe clock 24 through gate 25 to the scanner ring steps the scanner ringto the WRT-1 (write 1) stage. This same first pulse will flip theflip-flop 2, through the complement input, to its set state to generatethe first WRT PULSE. The set state of FFZ conditions gate 37. Theturning on of WRT-1 stage in the scanner ring provides through the writedriver associated therewith a one-half select current through the firstrow of cores. At the same time, the information stored in the seven-bitdrum register 27 supplies one-half select current to selected columns ofcores through the corresponding write drivers 29-35. The first WRT PULSEmakes this possible since it is supplied in parallel to all of thesewrite drivers 29 through to condition these write drivers. The first rowof cores then receives the contents of register 27; that is, the firstword transferred from the computer. This Write cycle requires onemicrosecond. The line AUDIO SAMPLE from AND gate 26 is down andtherefore inhibits the decoding matrix 36 so that the contents of theregister 27 do not affect said matrix and the analog gates connected tothe output of said matrix.

The second clock pulse through gate 25 passes through gate 37 which isconditioned by the set state of FF2. Thi second pulse is fed to thecomplementing input of FFZ and resets FFZ but not before said secondpulse gets through gate 37 to delay unit 38. This unit emits DRUMREGISTER RESET pulse shortly thereafter to reset register 27 through ORgate 39. The pulse output from OR gate 39 also passes through AND gate40, conditioned by READ INHIBIT LEVEL, to supply the computer the signalWORD DEMAND. This causes the computer to transfer the second computerword to register 27. The second clock pulse steps the scanner ring toRD-2. The third clock pulse accomplishes the same as the first clockpulse with respect to said second computer word.

This process continues repetitively and the scanner ring is continuouslystepped in this manner until the last thereof, namely, WRT50, is turnedon. At this time the final word from the computer, the fiftieth word inthis case, is stored in the last row of cores in the array 23.

(2) Readout from word memory The turning on of stage WRT- generates thesignal WRT-50 which is fed to ilip-fiop 3 to reset said flip-flop tounblock AND gate 26. This occurs on the th micro-second pulse. Theresetting of llip-ilop 3 brings down the line READ INHIBIT LEVEL. Thisline through OR gate 50, controls the operation of the output senseamplifiers 4l 47 associated with the array 23, to inhibit theseamplifiers during loading of the array 23 when it is up. The next pulse(the 101st) that is fed to the scanner ring returns the ring to the RD-lstage. This supplies full reset current to the row 1 cores and thesecores are thereby read out through the sense amplifiers 41 through 47,inclusive, and word 1 address stored in register 27. The 102ml pulse toscanner ring 28 steps the ring to WRT-L AND gate 26 being conditioned byfliptlop 3 in its reset state now passes this l02nd pulse to provide thefirst AUDIO SAMPLE pulse to the matrix 36. This sample pulse will permitthe contents of register 27 to raise one of the lines at the outputthereof, said line continuing in this state for the duration of theAUDIO SAMPLE pulse. Let us assume that it raises line 48. This then willcondition word gate 1 (WGI) which is associated with the output of wordamplifier l (WAI) which in turn is ussociatcd with the audio word storedin truck I of the word drum 10. The conditioning of word gate 1 byraising of output line 48 from matrix 36 will gate to the bus 11 aportion of the audio signal on track 1. It will suppy this portion toall of the gates 12 through 15, inclusive, for the 50 output channels.However, only AND 12 is conditioned by the WRT-1 pulse and this gatepasses the audio sample to channel 1. The WRT-1 pulse laso writes theaddress in drum register 27 back into row 1 of the word memory 23.During this rewriting, the sense amplifiers 41-47 are inhibited by theWRT pulse applied to the sense amplifier through OR gate 50.

The scanner ring 28 continues to step through its stages, each of whichcontrols the transfer of an address from word memory to drum register,the conditioning of one of the audio gates WGl-WG128, the conditioningof one of the analog gates l2-15 and the subsequent rewriting of theaddress back into the word memory. After stepping through the WRT50stage, the ring steps to the RD1 stage and the cycle, which occupies 100micro-seconds, is repeated.

This process of reading out from the core array to the register 27 andthen decoding by the matrix 36 continues for one complete revolution ofthe word drum. At the end of this complete revolution the first word ofa message has been supplied to each of the output channels, and ofcourse these first words may be entirely different and usually are in astock quotation system. During the construction of each word in theoutput channels, the audio tracks associated with each of the outputchannels are sampled once each 100 micro-seconds. If it is consideredthat the drum rotates once each second, then that means that each audiosignal is sampled ten thousand times. Therefore, the reproduction of thesignals on the track is quite complete.

When the drum has completed one revolution, the audio reproduction ofthe words on each of the output channels is complete and the occurrenceof the drum sync pulse signals the computer that another group of 50words to be read out on each of the output channels should be loadedinto the word memory. Upon occurrence of the drum sync pulse, theloading process described previously is repeated until the entiremessage for each channel has been completely composed. Said messages maybe repeated, changed, or staggered as desired.

In some cases a word of considerable length may be called for, i.e., onewhich can not be stored completely on one drum track. In this event, thefirst part of the word is stored on one track and the remaining part orparts on other tracks. These other tracks may or may not have otherwords or parts thereof stored thereon. The system can be programmed sothat during one revolution the first part of this long word is read outand then during successive revolutions the remaining part or parts areread out.

Also all messages need not be started at the same time. Some may startat the first revolution and others at selected succeeding revolutions.Programming of the system accommodates this procedure.

While there have been shown and described and pointed out thefundamental novel features of the invention as applied to the preferredembodiment, it will be understood that various omissions andsubstitutions and changes in the form and details of the deviceillustrated and in its operation may be made by those skilled in the artwithout departing from the spirit of the invention. It is the intention,therefore, to be limited only as indicated by the scope of the followingclaims.

What is claimed is:

1. A system for simultaneously composing speech messages in a pluralityof output channels, said messages being composed of at least one word,said system comprising word storage means for concurrently storing aplurality of words in the form of audio signals at discrete addresses,address storage means to store concurrently a series of selecteddiscrete addresses; output channel gating mean to condition said outputchannels in accordance with a repeated time multiplex sequence, toreceive portions of said audio signals, the time duration of one suchmultiplex sequence being a small fraction of the time required to readout the audio signal stored at any one of said addresses; and meansincluding said word address storage means operating synchronously withsaid time multiplex sequence to gate portions of the audio signalsstored at said series of selected addresses individually andsequentially to said output channel gating means; whereby saidpredetermined repetitive sequence of addressing and gating results inthe composition of said speech messages in each of said output channels.

2. The system recited in claim 1 wherein the word storage device is arotating magnetic drum, said audio signals being stored in discretetracks on said drum, and means to read the audio signals stored in eachof said discrete tracks and to transmit said signals to said outputchannel gating means.

3. The system recited in claim 1 and an external source of addressesspecifying words composing the speech messages for said plurality ofoutput channels.

4. The system recited in claim 3 wherein said address storage means is amagnetic core memory, means for transferring a plurality of addressesfrom said external source of addresses to said magnetic core memory,each of said addresses specifying a word to be transmitted on aparticular one of said plurality of output channels, and means torepetitively read each of said addresses out of said magnetic corememory and to repetitively restore each of said read out addresses intosaid magnetic core memory in accordance with said predetermined timemultiplex sequence, said means to address said Word storage means beingenabled by said read out addresses.

5. A system for simultaneously composing speech mes sages in a pluralityof output channels, said messages being composed of at least one word,said system comprising an external source of addresses, each of saidaddresses specifying a particular word to be transmitted oncorresponding ones of said output channels, a magnetic drum having aplurality of drum tracks, means for storing word in the form of audiosignals in discrete tracks of said magnetic drum, a word address storagedevice, means to transfer a plurality of addresses from said externalsource of addresses to said word address storage device, means operatingsubsequently to the transfer of said plurality of addresses forsequentially and repetitively reading said addresses out of said wordstorage device in accordance with a predetermined time multiplexsequence, means to condition said output channels sequentially toreceive said words in the form of audio signals in accordance with saidpredetermined sequence, and means to gate portions of said audio signalsfrom said drum tracks to said output channels during each multiplexsequence, said last named means being enabled by the addresses read outof said word address storage device.

6. The system recited in claim 5 wherein said word address storagedevice includes a magnetic core memory and said means for selectivelyand repetitively reading said addresses out of said memory includes ascanner ring, said scanner ring being connected to said magnetic corememory so as to selectively address different groups of said cores insaid memory.

References Cited by the Examiner UNITED STATES PATENTS ROBERT H. ROSE,Primary Examiner. L. MILLER ANDRUS, Examiner.

1. A SYSTEM FOR SIMULTANEOUSLU COMPOSING SPEECH MESSAGES IN A PLURALITYOF OUTPUT CHANNELS, SAID MESSAGES BEING COMPOSED OF AT LEAST ONE WORD,SAID SYSTEM COMPRISING WORD STORAGE MEANS FOR CONCURRENTLY STORING APLURALITY OF WORDS IN THEW FORM OF AUDIO SIGNALS AT DISCRETE ADDRESSES,ADDRESS STORAGE MEANS TO STORE CONCURRENTLY A SERIES OF SELECTEDDISCRETE ADDRESSES; OUTPUT CHANNEL GATING MEANS TO CONDITION SAID OUTPUTCHANNELS IS ACCORDANCE WITH A REPEATED TIME MULTIPLEX SEQUENCE, TORECEIVE PORTIONS OF SAID AUDIO SIGNALS, THE TIME DURATION OF ONE SUCHMULTIPLEX SEQUENCE BEING A SMALL FRACTION OF THE TIME REQUIRED TO READOUT THE AUDIO SIGNAL STORED AT ANY ONE OF SAID ADDRESSES; AND MEANSINCLUDING SAID WORD ADDRESS STORAGE MEANS OPERATING SYNCHRONOUSLY WITHSAID TIME MULTIPLEX SEQUENCE TO GATE PORTIONS OF THE AUDIO SIGNALSSTORED AT SAID SERIES OF SELECTED ADDRESSES INDIVIDUALLY ANDSEQUENTIALLY TO SAID OUTPUT CHANNEL GATING MEANS; WHEREBY SAIDPREDETERMINED REPETITIVE SEQUENCE OF ADDRESSING AND GATING RESULT IN THECOMPOSITION OF SAID SPEECH MESSAGES IN EACH OF SAID OUTPUT CHANNELS.